Networks-on-Chip (NoCs), for on-die communication between cores, are important in enabling scalable performance as the number of cores and intellectual property (IP) blocks increases in multi-core processors. In such instances, communication between components becomes the key power and performance limiter. NoCs enable efficient sharing of on-chip wiring resources for communication with routers to control and arbitrate the flow of data between communicating components.
NoCs transport data across chip between cores or other logic blocks. Latency is a critical performance metric, and is measured as the total delay through a network. A network with no traffic or arbitration overhead sends data at wire speeds (only interconnect and repeaters). In order to approach this latency, circuit-switched NoCs remove intra-route storage overhead. Furthermore, hybrid packet/circuit-switched NoCs move arbitration to a packet-switched stage to improve resource utilization. The critical path through the packet-switched portion of a router in these networks may involve several operations such as: i) latch data if needed, ii) decode direction relative to the current router, iii) arbitrate to determine priority for competing transmissions at each output port, and iv) send data to next router.
Like reference numbers and designations in the various drawings indicate like elements.